1. 일 시 : 2020년 1월 20일(월)
2. 장 소 : Fraunhofer IZM Berlin Building 17, Room 060, Gustav-Meyer-Allee 25, 13355 Berlin, Germany

-Overview Fraunhofer IZM(Dr. Michael Toepper)
-Fraunhofer IZM – Cooperation Partner of the Technical University of Berlin
-IZM Außenstelle Hochfrequenz-Sensorsysteme Cottbus (IZM-HFSC) Special
-Focus on Terahertz Modules for Ultra-High Resolution Sensing
-Research Fab Microelectronics Germany – Technology

-Status FOPLP(Dr. Tanja Braun)
-WhatisLarge Area Panel Level Packaging?
-Panel Level Packaging Embedding technology
-Merging of technologies, materials and equipment from Wafer, PCB, LCD,… technologies
-Not really a question of size Fan-out Panel Level Packaging
-Mold embedding approach
-Processing on large area formats (>> Æ300/330 mm)
-Driven by cost reduction and potential for large ðSiPs

-Status of PCB Embedding(Dr. Lars Böttcher)

-Adaptive Processes for High Density Panel Level Packaging
-Die-First Fan-Out Packaging – Yield Challenge
-PLP Laminate Embedding – German Project PEKOS
-Process Steps – Embedding into PCB Core
-Fraunhofer IZM’s Panel Level Packaging Consortia

-Updated status of Jisso Korea Council regarding embedding technology(Hyunho Kim)
-Current status of packaging integration R&D center for semiconductor convergence device and FODEM introduction Additional R&D status

-Updated status of Research Center for 3D-semiconductors
-Dr. Young-Gun Han (Fukuoka University)
-Dr. Shigehiro Hayashi (Research Center for 3D Semiconductors)
-Dr. Haruki Sueyoshi (Research Center for 3D Semiconductors)

-Current status of standardization activity on stacked electronic module
-1) Standardization initiatives of Fukuoka Jisso Consortium (FUJICO)
-Dr. Yoshihisa Katoh (Fukuoka University, Co-Convenor of IEC TC91WG6)
-2) Evaluation method of electrical connectivity – IEC 62878-2-602 and -603
-Mr. Satoshi Kojima (Kojima eDesign office, Convenor of IEC TC91WG12)